/**************************************************************************//**
 * @file           FE81001.h
 * @version        V1.0
 * $Revision:      1.0 $
 * $Date:          2021/04/08 $
 * @brief          Main function
 * @Author         
 * @ContactInfo    
 *
 * @note
 *
 * Copyright (C) 1998 Elite Semiconductor Memory Technology Corp.
 * All rights reserved.
 *
 ******************************************************************************/


#ifndef __FE81001_H__
#define __FE81001_H__


/*
 * Interrupt Vectors , ISR_ADDR = (ISR_NO+1)*3
 */
#define ISR_EINT0             0                 // 0x03
#define ISR_EINT1             1                 // 0x0B
#define ISR_EINT2             2                 // 0x13
#define ISR_EINT3             3                 // 0x1B
#define ISR_LVD               4                 // 0x23
#define ISR_SDM               5                 // 0x2B
#define ISR_RTC               6                 // 0x33
#define ISR_WDT               7                 // 0x3B
#define ISR_TMR0              8                 // 0x43
#define ISR_TMR1              9                 // 0x4B
#define ISR_TMR2              10                // 0x53
#define ISR_I2C               11                // 0x5B
#define ISR_UART              12                // 0x63
#define ISR_SPI               13                // 0x6B
#define ISR_CAP               14                // 0x73
//#define                       15                // 0x7B


/*
 * ==========================================================================
 * ----------- Processor and Core Peripheral Section ------------------------
 * ==========================================================================
 */

#include "system_FE81001.h"              /* FE81001 System */


/**
 * Initialize the system clock
 *
 * @param  none
 * @return none
 *
 * @brief  Setup the microcontroller system
 *         Initialize the PLL and update the SystemFrequency variable
 */
extern void SystemInit (void);


/******************************************************************************/
/*                Device Specific Peripheral registers structures             */
/******************************************************************************/
/*
 * Flash Memory Controller Register Definitions
 */
typedef struct {
	unsigned char fmccon;              // 0
	unsigned char fmccmd;              // 1
	unsigned char fmcadr[2];           // 2~3
	unsigned char fmcdata[2];          // 4~5
	unsigned char fmcstat;             // 6
	unsigned char fmccksum[2];         // 7~8
} xdata *fmc_reg_p;

/*
 * System Management Unit Register Definitions
 */
typedef struct {
	unsigned char PNID[4];             // 0~3
	unsigned char rstsrc;              // 4
	unsigned char sysrstc;             // 5
	unsigned char perrstc[2];          // 6~7
	unsigned char p0ctrl[2];           // 8~9
	unsigned char reserved0;
	unsigned char p0drv;               // B
	unsigned char p0ms[3];             // C~E
	unsigned char p0dout0;             // F
	unsigned char p0dout1;             // 10
	unsigned char p0dout2;             // 11
	unsigned char p0dout3;             // 12
	unsigned char p0dout4;             // 13
	unsigned char p0dout5;             // 14
	unsigned char p0dout6;             // 15
	unsigned char p0dout7;             // 16
	unsigned char p0mask;              // 17
	unsigned char p0dout;              // 18
	unsigned char p0din;               // 19
	unsigned char p1ctrl[2];           // 1A~1B
	unsigned char reserved1;
	unsigned char p1drv;               // 1D
	unsigned char p1ms[3];             // 1E~20
	unsigned char p1dout0;             // 21
	unsigned char p1dout1;             // 22
	unsigned char p1dout2;             // 23
	unsigned char p1dout3;             // 24
	unsigned char p1dout4;             // 25
	unsigned char p1dout5;             // 26
	unsigned char p1dout6;             // 27
	unsigned char p1dout7;             // 28
	unsigned char p1mask;              // 29
	unsigned char p1dout;              // 2A
	unsigned char p1din;               // 2B
	unsigned char p2ctrl[2];           // 2C~2D
	unsigned char reserved2;
	unsigned char p2drv;               // 2F
	unsigned char p2ms[3];             // 30~32
	unsigned char p2dout0;             // 33
	unsigned char p2dout1;             // 34
	unsigned char p2dout2;             // 35
	unsigned char p2dout3;             // 36
	unsigned char p2dout4;             // 37
	unsigned char p2dout5;             // 38
	unsigned char p2dout6;             // 39
	unsigned char p2dout7;             // 3A
	unsigned char p2mask;              // 3B
	unsigned char p2dout;              // 3C
	unsigned char p2din;               // 3D
	unsigned char p3ctrl[2];           // 3E~3F
	unsigned char reserved3;
	unsigned char p3drv;               // 41
	unsigned char p3ms[3];             // 42~44
	unsigned char p3dout0;             // 45
	unsigned char p3dout1;             // 46
	unsigned char p3dout2;             // 47
	unsigned char p3dout3;             // 48
	unsigned char p3dout4;             // 49
	unsigned char p3dout5;             // 4A
	unsigned char p3dout6;             // 4B
	unsigned char p3dout7;             // 4C
	unsigned char p3mask;              // 4D
	unsigned char p3dout;              // 4E
	unsigned char p3din;               // 4F
	unsigned char tmrstall;            // 50
	unsigned char ramctrl;             // 51
} xdata *smu_reg_p;

typedef struct {
    unsigned char gpio_ctrl[2];
	unsigned char reserved0;
	unsigned char gpio_drv;
	unsigned char gpio_ms[3];
	unsigned char gpio_dout0;
	unsigned char gpio_dout1;
	unsigned char gpio_dout2;
	unsigned char gpio_dout3;
	unsigned char gpio_dout4;
	unsigned char gpio_dout5;
	unsigned char gpio_dout6;
	unsigned char gpio_dout7;
	unsigned char gpio_mask;
	unsigned char gpio_dout;
	unsigned char gpio_din;
    
} xdata *gpio_reg_p;

/*
 * Clock Control Register Definitions
 */
typedef struct {
	unsigned char clken;               // 0
	unsigned char clkstb;              // 1
	unsigned char clksel;              // 2
	unsigned char rsbpclkc;            // 3
	unsigned char rsbepclkc[3];        // 4~6
	unsigned char rsbpclkdiv;          // 7
	unsigned char rsbepclkdiv[2];      // 8~9
	unsigned char pmcon;               // 10
	unsigned char reserved[5];         // 11~15
	unsigned char clktrim;             // 16
} xdata *clkctrl_reg_p;

/*
 * Interrupt Control Register Definitions
 */
typedef struct {
	unsigned char int_gmask;           // 0
	unsigned char eint_ctrl;           // 1
	unsigned char eint_en;             // 2
	unsigned char eint_dbctrl;         // 3
	unsigned char eint_stat;           // 4
	unsigned char int_stat0;           // 5
	unsigned char int_stat1;           // 6
	unsigned char irq_num;             // 7
	unsigned char irq_clr;             // 8 (W1C)
} xdata *intc_reg_p;

/*
 * Delta-Sigma Control Register Definitions
 */
typedef struct {
	unsigned char  rawdata[3];         // 0~2
	unsigned char  clbdata[3];         // 3~5
	unsigned char  clbgain0[3];        // 6~8
	unsigned char  clbos0[3];          // 9~B
	unsigned char  clbof0[3];          // C~E
	unsigned char  clbgain1[3];        // F~11
	unsigned char  clbos1[3];          // 12~14
	unsigned char  clbof1[3];          // 15~17
	unsigned char  osr;                // 18
	unsigned char  inmux;              // 19
	unsigned char  rmux;               // 1A
	unsigned char  pgaset;           // 1B
	unsigned char  encfg;             // 1C
	unsigned char  adcset;             // 1D
	unsigned char  conf;             // 1E
	unsigned char  intstat;            // 1F
} xdata *sdm_reg_p;

typedef struct {
	unsigned char  entest;             // 0x80
} xdata *sdm_tm_reg_p;

/*
 * Analog IP Register Definitions
 */
typedef struct {
	unsigned char    cmpcfg;           // 0
	unsigned char    cmpres;           // 1
	unsigned char    lvdcfg;           // 2
	unsigned char    lvdien;           // 3
	unsigned char    pwrcfg;           // 4
	unsigned char    igen_ctrl;            // 5
	unsigned char    igen1;        // 6
	unsigned char    igen2;       // 7
	unsigned char    igentrim1;       // 8
	unsigned char    igentrim2;       // 9
	unsigned char    bg_trim;          // A
} xdata *anac_reg_p;

/*
 * RTC Register Definitions
 */
typedef struct {
	unsigned char    cnt_sec;          // 0
	unsigned char    cnt_min;          // 1
	unsigned char    cnt_hour;         // 2
	unsigned char    cnt_day;          // 3
	unsigned char    alm_sec;          // 4
	unsigned char    alm_min;          // 5
	unsigned char    alm_hour;         // 6
	unsigned char    rtc_ctrl;         // 7
	unsigned char    rtc_stat;         // 8
	unsigned char    write_done;       // 9
} xdata *rtc_reg_p;

/*
 * Watchdog Register Definitions
 */
typedef struct {
	unsigned char    ctrl[2];          // 0~1
	unsigned char    restart;          // 2
	unsigned char    writeen;          // 3
	unsigned char    status;           // 4
} xdata *wdt_reg_p;

/*
 * I2C Control Register Definitions
 */
typedef struct {
	unsigned char    hw_cfg;           // 0
	unsigned char    int_en[2];        // 1~2
	unsigned char    int_st[2];        // 3~4
	unsigned char    slv_adr[2];       // 5~6
	unsigned char    i2c_dat;          // 7
	unsigned char    datcnt;           // 8
	unsigned char    i2c_ctrl;         // 9
	unsigned char    i2c_cmd;          // 10
	unsigned char    i2c_setup[4];     // 11~14
} xdata *i2c_reg_p;

/*
 * UART Control Register Definitions
 */
typedef struct {
	unsigned char    hw_cfg;           // 0
	unsigned char    osr_ctrl;         // 1
	unsigned char    bufdat_dll;       // 2
	unsigned char    ier_dlm;          // 3
	unsigned char    iir_fcr;          // 4
	unsigned char    line_ctrl;        // 5
	unsigned char    modem_ctrl;       // 6
	unsigned char    line_stat;        // 7
	unsigned char    modem_stat;       // 8
} xdata *uart_reg_p;

/*
 * LCM Control Register Definitions
 */
typedef struct {
	unsigned char control0;            // 0,RW
	unsigned char control1;            // 1,RW
	unsigned char reserved[14];        // 2~15
	unsigned char frambuf[20];         // 16~35,RW
} xdata *lcm_reg_p;

/*
 * TCK Control Register Definitions
 */
typedef struct {
	unsigned char control0;            // 0,RW
	unsigned char control1;            // 1,RW
	unsigned char threshold0;          // 2,RW
	unsigned char threshold1;          // 3,RW
	unsigned char wait0;               // 4,RW
	unsigned char wait1;               // 5,RW
	unsigned char level0;              // 6,R
	unsigned char level1;              // 7,R
	unsigned char int_stat;            // 8,RW (Write 1 Clear)
	unsigned char reserved[7];         // 9~15
	unsigned char ch0count[2];         // 16~17,R
	unsigned char ch1count[2];         // 18~19,R
	unsigned char ch0baseline[2];      // 20~21,R
	unsigned char ch1baseline[2];      // 22~23,R
} xdata *tck_reg_p;

/*
 * TMR0 Control Register Definitions
 */
typedef struct {
	unsigned char inten;               // 0,RW
	unsigned char int_stat;            // 1,RW
	unsigned char chen;                // 2,RW
	unsigned char chctrl[2];           // 3~4,RW
	unsigned char reload0[4];          // 5~8,RW
	unsigned char reload1[4];          // 9~12,RW
	unsigned char counter0[4];         // 13~16,R
	unsigned char counter1[4];         // 17~20,R
} xdata *tmr0_reg_p;

/*
 * TMR1 Control Register Definitions
 */
typedef struct {
	unsigned char inten;               // 0,RW
	unsigned char int_stat;            // 1,RW
	unsigned char chen;                // 2,RW
	unsigned char chctrl[2];           // 3~4,RW
	unsigned char reload0[4];          // 5~8,RW
	unsigned char reload1[4];          // 9~12,RW
	unsigned char counter0[4];         // 13~16,R
	unsigned char counter1[4];         // 17~20,R
} xdata *tmr1_reg_p;

/*
 * TMR2 Control Register Definitions
 */
typedef struct {
	unsigned char inten;               // 0,RW
	unsigned char int_stat;            // 1,RW
	unsigned char chen;                // 2,RW
	unsigned char chctrl[2];           // 3~4,RW
	unsigned char reload0[4];          // 5~8,RW
	unsigned char reload1[4];          // 9~12,RW
	unsigned char counter0[4];         // 13~16,R
	unsigned char counter1[4];         // 17~20,R
} xdata *tmr2_reg_p;

/*
 * SPI Control Register Definitions
 */
typedef struct {
	unsigned char trans_fmt[2];     // 0~1
	unsigned char trans_ctrl[4];    // 2~5
	unsigned char spi_cmd;          // 6
	unsigned char spi_adr[3];       // 7~9
	unsigned char spi_dat;          // 10
	unsigned char spi_ctrl[3];      // 11~13
	unsigned char spi_stat[3];      // 14~16
	unsigned char int_en;           // 17
	unsigned char int_stat;         // 18
	unsigned char intf_timing[2];   // 19~20
	unsigned char slv_stat[3];      // 21~23
	unsigned char slv_rcvcnt[2];    // 24~25
	unsigned char slv_tsmcnt[2];    // 26~27
	unsigned char spi_cfg;          // 28
} xdata *spi_reg_p;

/*
 * MFA Control Register Definitions
 */
typedef struct {
	unsigned char mul_ctrl;            // 0
	unsigned char mulp[2];             // 1~2
	unsigned char mulc[2];             // 3~4
	unsigned char prod[4];             // 5~8
	unsigned char fp_ctrl;             // 9
	unsigned char fp_mulp[4];          // 10~13
	unsigned char fp_mulc[4];          // 14~17
	unsigned char fp_prod[4];          // 18~21
	unsigned char fp_stat;             // 22
	unsigned char log_indat[4];        // 23~26,RW
	unsigned char log_outdat[4];       // 27~30,RW
	unsigned char log_stat;            // 31
} xdata *mfa_reg_p;

/*
 * CAP Control Register Definitions
 */
typedef struct {
	unsigned char prescale;            // 0
	unsigned char lpf_sel;             // 1
	unsigned char mode;                // 2
	unsigned char inten;               // 3
	unsigned char cap_ctrl;            // 4
	unsigned char reserved0;           // 5
	unsigned char cap0_cnt[2];         // 6~7
	unsigned char cap1_cnt[2];         // 8~9
	unsigned char cap2_cnt[2];         // 10~11
	unsigned char cap3_cnt[2];         // 12~13
	unsigned char reserved1;           // 14
	unsigned char capintf;             // 15
} xdata *cap_reg_p;


/******************************************************************************/
/*                         Peripheral memory map                              */
/******************************************************************************/
/* Stystem base address */
#define FLASH_BASE          (0x0000)                     // 32KB, 0x0000~0x7FFF -> FE81001 uses 8KB (0x0000~0x1FFF)
#define SRAM_BASE           (0x8000)                     // 8KB , 0x8000~0x9FFF -> FE81001 uses 2KB
#define RSBS_BASE           (0xA000)                     // 16KB, 0xA000~0xDFFF
#define RSBSE_BASE          (0xE000)                     // 8KB,  0xE000~0xFFFF

/*
 * RSBS Scope
 */
#define FMC_BASE            (RSBS_BASE  + 0x3000)        // 0xD000

 /*
 * RSBS Scope
 */
#define SMU_BASE            (RSBSE_BASE         )        // 0xE000
#define GPIO_BASE           (SMU_BASE   + 0x0008)        // 0xE008
#define GPIOA_BASE          (GPIO_BASE          )        // 0xE008
#define GPIOB_BASE          (GPIO_BASE  + 0x0012)        // 0xE01A
#define GPIOC_BASE          (GPIO_BASE  + 0x0024)        // 0xE02C
#define GPIOD_BASE          (GPIO_BASE  + 0x0036)        // 0xE03E

#define CLKCTRL_BASE        (RSBSE_BASE + 0x0200)        // 0xE200

#define INTC_BASE           (RSBSE_BASE + 0x0400)        // 0xE400

#define SDM_BASE            (RSBSE_BASE + 0x0600)        // 0xE600
#define SDMTM_BASE          (SDM_BASE   + 0x0080)        // 0xE680

#define ANAC_BASE           (RSBSE_BASE + 0x0800)        // 0xE800

#define RTC_BASE            (RSBSE_BASE + 0x0A00)        // 0xEA00

#define WDT_BASE            (RSBSE_BASE + 0x0C00)        // 0xEC00

#define I2C_BASE            (RSBSE_BASE + 0x0E00)        // 0xEE00

#define UART_BASE           (RSBSE_BASE + 0x1000)        // 0xF000

#define LCM_BASE            (RSBSE_BASE + 0x1200)        // 0xF200

#define CAP_BASE            (RSBSE_BASE + 0x1400)        // 0xF400

#define TMR0_BASE           (RSBSE_BASE + 0x1600)        // 0xF600

#define TMR1_BASE           (RSBSE_BASE + 0x1800)        // 0xF800

#define TMR2_BASE           (RSBSE_BASE + 0x1A00)        // 0xFA00

#define SPI_BASE            (RSBSE_BASE + 0x1C00)        // 0xFC00

#define MFA_BASE            (RSBSE_BASE + 0x1E00)        // 0xFE00

/******************************************************************************/
/*                         Peripheral declaration                             */
/******************************************************************************/
/*
 * RSBS Scope
 */
#define FMC                 ((fmc_reg_p)     FMC_BASE)

 /*
 * RSBS Scope
 */
#define SMU                 ((smu_reg_p)     SMU_BASE)
#define PA                  ((gpio_reg_p)    GPIOA_BASE)
#define PB                  ((gpio_reg_p)    GPIOB_BASE)
#define PC                  ((gpio_reg_p)    GPIOC_BASE)
#define PD                  ((gpio_reg_p)    GPIOD_BASE)

#define CLKC                ((clkctrl_reg_p) CLKCTRL_BASE)

#define INTC                ((intc_reg_p)    INTC_BASE)

#define SDM                 ((sdm_reg_p)     SDM_BASE)
#define SDMTM               ((sdm_tm_reg_p)  SDMTM_BASE)

#define ANA                 ((anac_reg_p)    ANAC_BASE)

#define RTC                 ((rtc_reg_p)     RTC_BASE)

#define WDT                 ((wdt_reg_p)     WDT_BASE)

#define I2C                 ((i2c_reg_p)     I2C_BASE)

#define UART                ((uart_reg_p)    UART_BASE)

#define LCM                 ((lcm_reg_p)     LCM_BASE)

#define CAP                 ((cap_reg_p)     CAP_BASE)

#define TMR0                ((tmr0_reg_p)    TMR0_BASE)

#define TMR1                ((tmr1_reg_p)    TMR1_BASE)

#define TMR2                ((tmr2_reg_p)    TMR2_BASE)

#define SPI                 ((spi_reg_p)     SPI_BASE)

#define MFA                 ((mfa_reg_p)     MFA_BASE)

/******************************************************************************/
/*                         Misc. declaration                                  */
/******************************************************************************/
typedef volatile unsigned char  vu8;
typedef volatile unsigned short vu16;
typedef volatile unsigned long  vu32;

#define M8(adr)  (*((vu8  *) (adr)))
#define M16(adr) (*((vu16 *) (adr)))
#define M32(adr) (*((vu32 *) (adr)))

#define outpw(port,value)	*((volatile unsigned int *)(port))=value
#define inpw(port)			(*((volatile unsigned int *)(port)))
#define outpb(port,value)	*((volatile unsigned char *)(port))=value
#define inpb(port)			(*((volatile unsigned char *)(port)))
#define outps(port,value)	*((volatile unsigned short *)(port))=value
#define inps(port)			(*((volatile unsigned short *)(port)))

#define GET_BIT(x, bit_) ((x & (1 << bit_)) >> bit_)   /* ¨ú²Äbit¦ì */

#define HHH(w)           ((unsigned char)(w >> 24))
#define HH(w)           ((unsigned char)(w >> 16))
#define H(w)           ((unsigned char)(w >> 8))
#define L(w)           ((unsigned char)(w&0xff))

#define TRUE	   	1
#define FALSE   	0

#define ENABLE      1
#define DISABLE     0

// Define one bit mask
#define BIT0	0x00000001
#define BIT1	0x00000002
#define BIT2	0x00000004
#define BIT3	0x00000008
#define BIT4	0x00000010
#define BIT5	0x00000020
#define BIT6	0x00000040
#define BIT7	0x00000080
#define BIT8	0x00000100
#define BIT9	0x00000200
#define BIT10	0x00000400
#define BIT11	0x00000800
#define BIT12	0x00001000
#define BIT13	0x00002000
#define BIT14	0x00004000
#define BIT15	0x00008000
#define BIT16	0x00010000
#define BIT17	0x00020000
#define BIT18	0x00040000
#define BIT19	0x00080000
#define BIT20	0x00100000
#define BIT21	0x00200000
#define BIT22	0x00400000
#define BIT23	0x00800000
#define BIT24	0x01000000
#define BIT25	0x02000000
#define BIT26	0x04000000
#define BIT27	0x08000000
#define BIT28	0x10000000
#define BIT29	0x20000000
#define BIT30	0x40000000
#define BIT31	0x80000000
#define BIT_All 0xFF


/*
*************************************************************************************
*  CLOCK 
*
*************************************************************************************
*/

//	Clock Source	Enable / Disable
#define HSRC_Enable()														CLKC->clken |= HSRCEN   // Default Enable
#define LSRCEN_Enable()											CLKC->clken |= LSRCEN    // Default Enable
#define XTALEN_Enable()											CLKC->clken |= XTALEN    // Default Enable

#define HSRC_Disable()													CLKC->clken &= (~HSRCEN)  
#define LSRCEN_Disable()											CLKC->clken &= (~LSRCEN)  
#define XTALEN_Disable()										CLKC->clken &= (~XTALEN) 

//	System Clock - Select Clock Source
#define High_Speed_Oscillator 								0
#define External_Crystal 													1
#define Low_Speed_Oscillator 								2
#define Set_SysClockSource(x) 							CLKC->clksel =  (CLKC->clksel & 0xF8) | x 

//	HPB Peripheral Clock Control
#define MUC_Clock_Enable()									CLKC->rsbpclkc  |= MCUEN    // Default Enable
#define HPB_Clock_Enable()										CLKC->rsbpclkc  |= HPBEN			// Default Enable
#define PFB_Clock_Enable()										CLKC->rsbpclkc  |= PFBEN			// Default Enable

#define MUC_Clock_Disable()								CLKC->rsbpclkc  &= (~MCUEN)
#define HPB_Clock_Disable()									CLKC->rsbpclkc  &= (~HPBEN)
#define PFB_Clock_Disable()										CLKC->rsbpclkc  &= (~PFBEN)

// Sysclk Div  8M /  CCLK_Div  (CCLK fot 8051 core)
#define 	CCLK_Div_1()														CLKC-> rsbpclkdiv &= 0xF0 ; CLKC-> rsbpclkdiv |= 0x01
#define 	CCLK_Div_2()														CLKC-> rsbpclkdiv &= 0xF0 ; CLKC-> rsbpclkdiv |= 0x02
#define 	CCLK_Div_3()														CLKC-> rsbpclkdiv &= 0xF0 ; CLKC-> rsbpclkdiv |= 0x03
#define 	CCLK_Div_4()														CLKC-> rsbpclkdiv &= 0xF0 ; CLKC-> rsbpclkdiv |= 0x04
#define 	CCLK_Div_5()														CLKC-> rsbpclkdiv &= 0xF0 ; CLKC-> rsbpclkdiv |= 0x05
#define 	CCLK_Div_6()														CLKC-> rsbpclkdiv &= 0xF0 ; CLKC-> rsbpclkdiv |= 0x06
#define 	CCLK_Div_7()														CLKC-> rsbpclkdiv &= 0xF0 ; CLKC-> rsbpclkdiv |= 0x07
#define 	CCLK_Div_8()														CLKC-> rsbpclkdiv &= 0xF0 ; CLKC-> rsbpclkdiv |= 0x08
#define 	CCLK_Div_9()														CLKC-> rsbpclkdiv &= 0xF0 ; CLKC-> rsbpclkdiv |= 0x09
#define 	CCLK_Div_10()														CLKC-> rsbpclkdiv &= 0xF0 ; CLKC-> rsbpclkdiv |= 0x0A
#define 	CCLK_Div_11()														CLKC-> rsbpclkdiv &= 0xF0 ; CLKC-> rsbpclkdiv |= 0x0B
#define 	CCLK_Div_12()														CLKC-> rsbpclkdiv &= 0xF0 ; CLKC-> rsbpclkdiv |= 0x0C
#define 	CCLK_Div_13()														CLKC-> rsbpclkdiv &= 0xF0 ; CLKC-> rsbpclkdiv |= 0x0D
#define 	CCLK_Div_14()														CLKC-> rsbpclkdiv &= 0xF0 ; CLKC-> rsbpclkdiv |= 0x0E
#define 	CCLK_Div_15()														CLKC-> rsbpclkdiv &= 0xF0 ; CLKC-> rsbpclkdiv |= 0x0F

// PCLK Div  CCLK /  PCLK Div  (PCLK for	APB)
#define		PCLK_Div_1()																CLKC-> rsbpclkdiv &= 0x0F ; CLKC-> rsbpclkdiv |= 0x10
#define 	PCLK_Div_2()																CLKC-> rsbpclkdiv &= 0x0F ; CLKC-> rsbpclkdiv |= 0x20
#define 	PCLK_Div_3()																CLKC-> rsbpclkdiv &= 0x0F ; CLKC-> rsbpclkdiv |= 0x30
#define 	PCLK_Div_4()																CLKC-> rsbpclkdiv &= 0x0F ; CLKC-> rsbpclkdiv |= 0x40
#define 	PCLK_Div_5()																CLKC-> rsbpclkdiv &= 0x0F ; CLKC-> rsbpclkdiv |= 0x50
#define 	PCLK_Div_6()																CLKC-> rsbpclkdiv &= 0x0F ; CLKC-> rsbpclkdiv |= 0x60
#define 	PCLK_Div_7()																CLKC-> rsbpclkdiv &= 0x0F ; CLKC-> rsbpclkdiv |= 0x70
#define 	PCLK_Div_8()																CLKC-> rsbpclkdiv &= 0x0F ; CLKC-> rsbpclkdiv |= 0x80
#define 	PCLK_Div_9()																CLKC-> rsbpclkdiv &= 0x0F ; CLKC-> rsbpclkdiv |= 0x90
#define 	PCLK_Div_10()															CLKC-> rsbpclkdiv &= 0x0F ; CLKC-> rsbpclkdiv |= 0xA0
#define 	PCLK_Div_11()															CLKC-> rsbpclkdiv &= 0x0F ; CLKC-> rsbpclkdiv |= 0xB0
#define 	PCLK_Div_12()															CLKC-> rsbpclkdiv &= 0x0F ; CLKC-> rsbpclkdiv |= 0xC0
#define 	PCLK_Div_13()															CLKC-> rsbpclkdiv &= 0x0F ; CLKC-> rsbpclkdiv |= 0xD0
#define 	PCLK_Div_14()															CLKC-> rsbpclkdiv &= 0x0F ; CLKC-> rsbpclkdiv |= 0xE0
#define 	PCLK_Div_15()															CLKC-> rsbpclkdiv &= 0x0F ; CLKC-> rsbpclkdiv |= 0xF0


/*
*************************************************************************************
*  IO PORT 
*
*************************************************************************************
*/

// Px Clock Enable

#define PORT_PA_Clock_Enable()  				            CLKC->rsbepclkc[1] |= PAEN
#define PORT_PB_Clock_Enable()  				          	CLKC->rsbepclkc[1] |= PBEN
#define PORT_PC_Clock_Enable()  				         	  CLKC->rsbepclkc[1] |= PCEN
#define PORT_PD_Clock_Enable()  				        	  CLKC->rsbepclkc[1] |= PDEN
#define PORT_PAPBPCPD_Clock_Enable()  			  CLKC->rsbepclkc[1] |= 0xF0
                                                                             
#define PORT_PA_Clock_Disable()  				        	 CLKC-->rsbepclkc[1] &= (~PAEN)
#define PORT_PB_Clock_Disable()  				        	 CLKC-->rsbepclkc[1] &= (~PBEN)
#define PORT_PC_Clock_Disable()  				        	 CLKC-->rsbepclkc[1] &= (~PCEN)
#define PORT_PD_Clock_Disable()  				        	 CLKC-->rsbepclkc[1] &= (~PDEN)
#define PORT_PAPBPCPD_Clock_Disable() 		 	 CLKC-->rsbepclkc[1] &= (~(0xF0))





// Set PA Pin-Mode

#define PORT_SetPAInput(x)												PA->gpio_ms[2] &= (~(x))   ;  PA->gpio_ms[1] &= (~(x)) ;       PA->gpio_ms[0] &= (~(x)); 
#define PORT_SetPAPushPull(x)									PA->gpio_ms[2] &= (~(x))   ;  PA->gpio_ms[1] &= (~(x)) ;       PA->gpio_ms[0] |= (x); 
#define PORT_SetPAOpenDrain(x)								PA->gpio_ms[2] &= (~(x))   ;  PA->gpio_ms[1] |= (x) ;              PA->gpio_ms[0] &= (~(x)); 
#define PORT_SetPAPullUp(x)										PA->gpio_ms[2] &= (~(x))   ;  PA->gpio_ms[1] |= (x) ; 					  PA->gpio_ms[0] |= (x);
#define PORT_SetPAHighImpendence(x)			PA->gpio_ms[2] |= (x)   			 ;  PA->gpio_ms[1] &= (~(x));		    PA->gpio_ms[0] &= (~(x));

// Set PB Pin-Mode

#define PORT_SetPBInput(x)												PB->gpio_ms[2] &= (~(x))   ;  PB->gpio_ms[1] &= (~(x)) ;       PB->gpio_ms[0] &= (~(x)); 
#define PORT_SetPBPushPull(x)									PB->gpio_ms[2] &= (~(x))   ;  PB->gpio_ms[1] &= (~(x)) ;       PB->gpio_ms[0] |= (x); 
#define PORT_SetPBOpenDrain(x)								PB->gpio_ms[2] &= (~(x))   ;  PB->gpio_ms[1] |= (x) ;              PB->gpio_ms[0] &= (~(x)); 
#define PORT_SetPBPullUp(x)										  PB->gpio_ms[2] &= (~(x))   ;  PB->gpio_ms[1] |= (x) ; 					    PB->gpio_ms[0] |= (x);
#define PORT_SetPBHighImpendence(x)			  PB->gpio_ms[2] |= (x)   			 ;  PB->gpio_ms[1] &= (~(x));		    PB->gpio_ms[0] &= (~(x));

// Set PC Pin-Mode

#define PORT_SetPCInput(x)												PC->gpio_ms[2] &= (~(x))   ;  PC->gpio_ms[1] &= (~(x)) ;       PC->gpio_ms[0] &= (~(x)); 
#define PORT_SetPCPushPull(x)									PC->gpio_ms[2] &= (~(x))   ;  PC->gpio_ms[1] &= (~(x)) ;       PC->gpio_ms[0] |= (x); 
#define PORT_SetPCOpenDrain(x)								PC->gpio_ms[2] &= (~(x))   ;  PC->gpio_ms[1] |= (x) ;              PC->gpio_ms[0] &= (~(x)); 
#define PORT_SetPCPullUp(x)										  PC->gpio_ms[2] &= (~(x))   ;  PC->gpio_ms[1] |= (x) ; 					    PC->gpio_ms[0] |= (x);
#define PORT_SetPCHighImpendence(x)			  PC->gpio_ms[2] |= (x)   			 ;  PC->gpio_ms[1] &= (~(x));		    PC->gpio_ms[0] &= (~(x));

// Set PD Pin-Mode

#define PORT_SetPDInput(x)												PD->gpio_ms[2] &= (~(x))   ;  PD->gpio_ms[1] &= (~(x)) ;       PD->gpio_ms[0] &= (~(x)); 
#define PORT_SetPDPushPull(x)									PD->gpio_ms[2] &= (~(x))   ;  PD->gpio_ms[1] &= (~(x)) ;       PD->gpio_ms[0] |= (x); 
#define PORT_SetPDOpenDrain(x)								PD->gpio_ms[2] &= (~(x))   ;  PD->gpio_ms[1] |= (x) ;              PD->gpio_ms[0] &= (~(x)); 
#define PORT_SetPDPullUp(x)										PD->gpio_ms[2] &= (~(x))   ;  PD->gpio_ms[1] |= (x) ; 					   PD->gpio_ms[0] |= (x);
#define PORT_SetPDHighImpendence(x)			PD->gpio_ms[2] |= (x)   			 ;  PD->gpio_ms[1] &= (~(x));		     PD->gpio_ms[0] &= (~(x));


// Set PAx as GPIO
#define PORT_SetPAGPIO(x)											PA->gpio_ctrl[1] &= (~(x)) ;				PA->gpio_ctrl[0] &= (~(x)) ;

// Set PBx as GPIO
#define PORT_SetPBGPIO(x)											  PB->gpio_ctrl[1] &= (~(x)) ;				PB->gpio_ctrl[0] &= (~(x)) ;

// Set PCx as GPIO 
#define PORT_SetPCGPIO(x)											  PC->gpio_ctrl[1] &= (~(x)) ;				PC->gpio_ctrl[0] &= (~(x)) ;

// Set PDx as GPIO
#define PORT_SetPDGPIO(x)											PD->gpio_ctrl[1] &= (~(x)) ;				PD->gpio_ctrl[0] &= (~(x)) ;

//	Get PAx Inpute Level  input(Bit)  = 0~7
#define Get_PAx_input(Bit)																			(PA->gpio_din & 1<<Bit)>>(Bit)

//	Get PBx Inpute Level	input(Bit) = 0~7
#define Get_PBx_input(Bit)																			(PB->gpio_din & 1<<Bit)>>(Bit)

//	Get PCx Inpute Level	input(Bit)  = 0~7
#define Get_PCx_input(Bit)																			(PC->gpio_din & 1<<Bit)>>(Bit)

//	Get PDx Inpute Level	input(Bit)  = 0~7
#define Get_PDx_input(Bit)																			(PD->gpio_din & 1<<Bit)>>(Bit)

//	Set PAx Output Level
#define PA0																										PA->gpio_dout0
#define PA1																										PA->gpio_dout1
#define PA2																										PA->gpio_dout2
#define PA3																										PA->gpio_dout3
#define PA4																										PA->gpio_dout4
#define PA5																										PA->gpio_dout5
#define PA6																										PA->gpio_dout6
#define PA7																										PA->gpio_dout7

//	Set PBx Output Level
#define PB0																										PB->gpio_dout0
#define PB1																										PB->gpio_dout1
#define PB2																										PB->gpio_dout2
#define PB3																										PB->gpio_dout3
#define PB4																										PB->gpio_dout4
#define PB5																										PB->gpio_dout5
#define PB6																										PB->gpio_dout6
#define PB7																										PB->gpio_dout7

//	Set PCx Output Level
#define PC0																										PC->gpio_dout0
#define PC1																										PC->gpio_dout1
#define PC2																										PC->gpio_dout2
#define PC3																										PC->gpio_dout3
#define PC4																										PC->gpio_dout4
#define PC5																										PC->gpio_dout5
#define PC6																										PC->gpio_dout6
#define PC7																										PC->gpio_dout7

//	Set PDx Output Level
#define PD0																										PD->gpio_dout0
#define PD1																										PD->gpio_dout1
#define PD2																										PD->gpio_dout2
#define PD3																										PD->gpio_dout3
#define PD4																										PD->gpio_dout4
#define PD5																										PD->gpio_dout5
#define PD6																										PD->gpio_dout6
#define PD7																										PD->gpio_dout7


/*
*************************************************************************************
*  UART
*
*************************************************************************************
*/

//	Enable UART Clock
#define  En_UART_clk()                                 CLKC->rsbepclkc[0] |= UARTEN

// Set PA6,PA7 Function
#define Set_PA6_Rx()																		PA->gpio_ctrl[1] &= (~BIT6) ; PA->gpio_ctrl[0] |= BIT6
#define Set_PA7_Tx()																		PA->gpio_ctrl[1] &= (~BIT7) ; PA->gpio_ctrl[0] |= BIT7

// Set BaudRate  Sys = 8MHz
#define Set_BaudRate_115200()															UART->osr_ctrl   = 0x0E;  UART->line_ctrl  = 0x80; UART->bufdat_dll = 0x05; UART->ier_dlm    = 0x00; UART->line_ctrl  = 0x00
#define Set_BaudRate_9600()																	UART->osr_ctrl   = 0x10;  UART->line_ctrl  = 0x80; UART->bufdat_dll = 0x34; UART->ier_dlm    = 0x00; UART->line_ctrl  = 0x00
#define Set_BaudRate_256000()															UART->osr_ctrl   = 0x10;  UART->line_ctrl  = 0x80; UART->bufdat_dll = 0x02; UART->ier_dlm    = 0x00; UART->line_ctrl  = 0x00

/*
*************************************************************************************
*  I2C
*
*************************************************************************************
*/

//	Enable I2C Clock
#define En_I2C_clk()																			CLKC->rsbepclkc[0] |= I2CEN

//	Set PA4,PA5 Function
#define Set_PA4_SDA()																PA->gpio_ctrl[1] &= (~BIT4) ; PA->gpio_ctrl[0] |= BIT4
#define Set_PA5_SCL()																  PA->gpio_ctrl[1] &= (~BIT5) ; PA->gpio_ctrl[0] |= BIT5

// Set  I2C speed
#define I2C_speed_400k_12M()										I2C->i2c_setup[1] = 0x0C;   I2C->i2c_setup[2] = 0x00;    I2C->i2c_setup[3] = 0x00;         
#define I2C_speed_400k_8M()											I2C->i2c_setup[1] = 0x06; I2C->i2c_setup[2] = 0x00;  I2C->i2c_setup[3] = 0x00;  

// I2C_control_reset
#define I2C_Control_Reset() 													I2C->i2c_cmd = 0x05; 							// Reset I2C control 

/*
*************************************************************************************
*  RTC
*
*************************************************************************************
*/

//	Enable RTC clock
#define En_RTC_clk()																			CLKC->rsbepclkc[0] |= RTCEN

// RTC clock source select
#define Low_speed_oscillator 								0x00
#define Low_speed_crystal 										0x08
#define Set_RTC_ClockSource(x) 						CLKC->clksel =  ( CLKC->clksel & (~RTCSRC) )  |  x 

//// RTC  Enable
//#define RTC_enable() 														RTC->rtc_ctrl  |=  RTCEN_ 

//// RTC	Disable
//#define RTC_disable() 														RTC->rtc_ctrl  &=  (~RTCEN_) 

//// RTC interrupt Enable
//#define RTC_INT_wakeup_enable() 						RTC->rtc_ctrl  |=  ALMWEN  // For wakeup from low power mode
//#define RTC_INT_alarm_enable() 							RTC->rtc_ctrl  |=  ALMIEN 
//#define RTC_INT_day_enable() 									RTC->rtc_ctrl  |=  DAYIEN 
//#define RTC_INT_hout_enable() 								RTC->rtc_ctrl  |=  HORIEN 
//#define RTC_INT_min_enable() 									RTC->rtc_ctrl  |=  MINIEN 
//#define RTC_INT_sec_enable() 									RTC->rtc_ctrl  |=  SECIEN 


/*
*************************************************************************************
*  WDT
*
*************************************************************************************
*/

//	Enable WDT clock
#define En_WDT_clk()																			CLKC->rsbepclkc[0] |= WDTEN

// Set WDT clock source  [1]
#define WDT_LSRC 																					0x00
#define WDT_PCLK 																				0x02

#define WDT_Set_clock_LSRC()																	WDT->ctrl[1] &= (~CLKSEL) ; WDT->ctrl[1] |=  WDT_LSRC
#define WDT_Set_clock_PCLK()																	WDT->ctrl[1] &= (~CLKSEL) ; WDT->ctrl[1] |=  WDT_PCLK


// Enable WDT Write Portect
#define En_WDT_WriteProtect()											WDT->writeen = WRITE_PROTECT
#define WRITE_PROTECT      0xA5
#define MAGIC_NUM          0x5A

// Set Reset time  [4:5]
#define RestTime 					0x30  

#define RT_x128 					0x00
#define RT_x256 					0x10
#define RT_x512 					0x20
#define RT_x1024 				0x30

#define Reset_Time_Period_x128()												WDT->ctrl[0] &= (~RestTime) ;  WDT->ctrl[0] |= RT_x128
#define Reset_Time_Period_x256()												WDT->ctrl[0] &= (~RestTime) ;  WDT->ctrl[0] |= RT_x256
#define Reset_Time_Period_x512()												WDT->ctrl[0] &= (~RestTime) ;  WDT->ctrl[0] |= RT_x512
#define Reset_Time_Period_x1024()											WDT->ctrl[0] &= (~RestTime) ;  WDT->ctrl[0] |= RT_x1024

// Set Interrupt time [0:2]
#define InterruptTime 					0x07 

#define IT_x64 							0x00
#define IT_x256 						0x01
#define IT_x1024 					0x02
#define IT_x2048 					0x03
#define IT_x4096 					0x04
#define IT_x8192 					0x05
#define IT_x16384 				0x06
#define IT_x32768 				0x07

#define Interrupt_Time_Period_x64()													WDT->ctrl[0] &= (~InterruptTime) ;  WDT->ctrl[0] |= IT_x64
#define Interrupt_Time_Period_x256()												WDT->ctrl[0] &= (~InterruptTime) ;  WDT->ctrl[0] |= IT_x256
#define Interrupt_Time_Period_x1024()								  			WDT->ctrl[0] &= (~InterruptTime) ;  WDT->ctrl[0] |= IT_x1024
#define Interrupt_Time_Period_x2048()								  			WDT->ctrl[0] &= (~InterruptTime) ;  WDT->ctrl[0] |= IT_x2048
#define Interrupt_Time_Period_x4096()								  			WDT->ctrl[0] &= (~InterruptTime) ;  WDT->ctrl[0] |= IT_x4096
#define Interrupt_Time_Period_x8192()								  			WDT->ctrl[0] &= (~InterruptTime) ;  WDT->ctrl[0] |= IT_x8192
#define Interrupt_Time_Period_x16384()							  			WDT->ctrl[0] &= (~InterruptTime) ;  WDT->ctrl[0] |= IT_x16384
#define Interrupt_Time_Period_x32768()							  			WDT->ctrl[0] &= (~InterruptTime) ;  WDT->ctrl[0] |= IT_x32768

// Reset Enable
#define WDT_Reset_Enable()																			WDT->ctrl[1] |= RSTEN
#define WDT_INTEN_Enable()																	WDT->ctrl[1] |= INTEN
#define WDT_WDTEN_Enable()																WDT->ctrl[1] |= _WDTEN

// Reset WDT(Clear WDT)
#define WDT_Reset() 																								WDT->writeen = WRITE_PROTECT; WDT->restart = MAGIC_NUM

/*
*************************************************************************************
*  Timer 0 - 2 channel
*
*************************************************************************************
*/

// Reload[0]-> Hbyte   Reload[1]-> Lbyte 

//**********Global Parameter**********//

// TIMERx CHx Mode Select
#define Mode_32bit_Timer		 								      	 1 
#define Mode_16bit_Timer 										       2
#define Mode_8bit_Timer 			 								       3
#define Mode_PWM							 								       4
#define Mode_Mix_PWM_16it_Timer	   		   6
#define Mode_Mix_PWM_8bit_Timer       		 7

// TIMERx Interrupt / Start  Enable
#define Ch0_Timer0  																		1
#define Ch0_Timer1  																		2
#define Ch0_Timer2  																		4
#define Ch0_Timer3  																		8
#define Ch1_Timer0  																		16
#define Ch1_Timer1  																		32
#define Ch1_Timer2  																		64
#define Ch1_Timer3  																		128

//***********************************//


// Timer0 clock source select 
#define Timer0_clock_PCLK()																CLKC->clksel &=  (~TMR0SRC)
#define Timer0_clock_LSRC()																CLKC->clksel    |= TMR0SRC

// Timer1 clock source select 
#define Timer1_clock_PCLK()																CLKC->clksel &=  (~TMR1SRC)
#define Timer1_clock_LSRC()																CLKC->clksel    |= TMR1SRC

// Timer2 clock source select 
#define Timer2_clock_PCLK()																CLKC->clksel &=  (~TMR2SRC)
#define Timer2_clock_LSRC()																CLKC->clksel    |= TMR2SRC

// Enable Time0 Clock
#define En_Timer0_clk()																					CLKC->rsbepclkc[1] |= TMR0EN

// Set_PB4_PWM0
#define Set_PB4_PWM0()                											PB->gpio_ctrl[1] &= (~BIT4) ; PB->gpio_ctrl[0] |= BIT4

// Set_PB5_PWM1
#define Set_PB5_PWM1()                											PB->gpio_ctrl[1] &= (~BIT5) ; PB->gpio_ctrl[0] |= BIT5

// Timer0 Clock_Div_number  [7:6]
#define Timer0_Div_4																							0x00
#define Timer0_Div_8																							0x40
#define Timer0_Div_16																						0x80
#define Timer0_Div_32																						0xC0

#define Timer0_clock_Div_4()															CLKC->rsbepclkdiv[0] &= (~0xC0) ;  CLKC->rsbepclkdiv[0] |= Timer0_Div_4;
#define Timer0_clock_Div_8()															CLKC->rsbepclkdiv[0] &= (~0xC0) ;  CLKC->rsbepclkdiv[0] |= Timer0_Div_8;
#define Timer0_clock_Div_16()														CLKC->rsbepclkdiv[0] &= (~0xC0) ;  CLKC->rsbepclkdiv[0] |= Timer0_Div_16;
#define Timer0_clock_Div_32()														CLKC->rsbepclkdiv[0] &= (~0xC0) ;  CLKC->rsbepclkdiv[0] |= Timer0_Div_32;

// Timer0	CH0  Select Mode
#define Timer0_CH0_Mode(x)															 TMR0->chctrl[0]  = x ; 

// Timer0	CH1  Select Mode
#define Timer0_CH1_Mode(x)															 TMR0->chctrl[1]  = x ; 

// Timer0 Interrupt Enable
#define  Timer0_Interrupt_Enable(x)											TMR0->inten |= x  

// Timer0 Interrupt Disable
#define  Timer0_Interrupt_Disable(x)										TMR0->inten &= (~x) 

//Timer0 Start Enable
#define  Timer0_Start_Enable(x)														TMR0->chen |= x  

//Timer0 Start Disable
#define  Timer0_Start_Disable(x)													TMR0->chen &= (~x)  


/*
*************************************************************************************
*  Timer 1 - 2 channel
*
*************************************************************************************
*/

// Timer1 clock source select 
#define Timer1_clock_PCLK()																CLKC->clksel &=  (~TMR1SRC)
#define Timer1_clock_LSRC()																CLKC->clksel    |= TMR1SRC

// Enable Time1 Clock
#define En_Timer1_clk()																					CLKC->rsbepclkc[1] |= TMR1EN

// Set_PB6_PWM2
#define Set_PB6_PWM2()                											PB->gpio_ctrl[1] &= (~BIT6) ; PB->gpio_ctrl[0] |= BIT6

// Set_PB7_PWM3
#define Set_PB7_PWM3()                											PB->gpio_ctrl[1] &= (~BIT7) ; PB->gpio_ctrl[0] |= BIT7

// Timer1 Clock_Div_number  [1:0]
#define Timer1_Div_4																							0x00
#define Timer1_Div_8																							0x01
#define Timer1_Div_16																						0x02
#define Timer1_Div_32																						0x03

#define Timer1_clock_Div_4()															CLKC->rsbepclkdiv[1] &= (~0x03) ;  CLKC->rsbepclkdiv[1] |= Timer1_Div_4;
#define Timer1_clock_Div_8()															CLKC->rsbepclkdiv[1] &= (~0x03) ;  CLKC->rsbepclkdiv[1] |= Timer1_Div_8;
#define Timer1_clock_Div_16()														CLKC->rsbepclkdiv[1] &= (~0x03) ;  CLKC->rsbepclkdiv[1] |= Timer1_Div_16;
#define Timer1_clock_Div_32()														CLKC->rsbepclkdiv[1] &= (~0x03) ;  CLKC->rsbepclkdiv[1] |= Timer1_Div_32;

// Timer1	CH0  Select Mode
#define Timer1_CH0_Mode(x)															 TMR1->chctrl[0]  = x ; 

// Timer1	CH1  Select Mode
#define Timer1_CH1_Mode(x)															 TMR1->chctrl[1]  = x ; 

// Timer1 Interrupt Enable
#define  Timer1_Interrupt_Enable(x)											TMR1->inten |= x  

// Timer1 Interrupt Disable
#define  Timer1_Interrupt_Disable(x)										TMR1->inten &= (~x) 

//Timer1 Start Enable
#define  Timer1_Start_Enable(x)														TMR1->chen |= x  

//Timer1 Start Disable
#define  Timer1_Start_Disable(x)													TMR1->chen &= (~x)  

/*
*************************************************************************************
*  Timer 2 - 2 channel
*
*************************************************************************************
*/

// Timer2 clock source select 
#define Timer2_clock_PCLK()																CLKC->clksel &=  (~TMR2SRC)
#define Time2_clock_LSRC()																	CLKC->clksel    |= TMR2SRC

// Enable Time2 Clock
#define En_Timer2_clk()																			CLKC->rsbepclkc[1] |= TMR2EN

// Set_PC0_PWM4
#define Set_PC0_PWM4()                										PC->gpio_ctrl[1] &= (~BIT0) ; PC->gpio_ctrl[0] |= BIT0

// Set_PC1_PWM5
#define Set_PC1_PWM5()                										PC->gpio_ctrl[1] &= (~BIT1) ; PC->gpio_ctrl[0] |= BIT1

// Timer2 Clock_Div_number  [3:2]
#define Timer2_Div_4																							0x00
#define Timer2_Div_8																							0x04
#define Timer2_Div_16																						0x08
#define Timer2_Div_32																						0x0C

#define Timer2_clock_Div_4()															CLKC->rsbepclkdiv[1] &= (~0x0C) ;  CLKC->rsbepclkdiv[1] |= Timer2_Div_4;
#define Timer2_clock_Div_8()															CLKC->rsbepclkdiv[1] &= (~0x0C) ;  CLKC->rsbepclkdiv[1] |= Timer2_Div_8;
#define Timer2_clock_Div_16()														CLKC->rsbepclkdiv[1] &= (~0x0C) ;  CLKC->rsbepclkdiv[1] |= Timer2_Div_16;
#define Timer2_clock_Div_32()														CLKC->rsbepclkdiv[1] &= (~0x0C) ;  CLKC->rsbepclkdiv[1] |= Timer2_Div_32;

// Timer2	CH0  Select Mode
#define Timer2_CH0_Mode(x)															 TMR2->chctrl[0]  = x ; 

// Timer2	CH1  Select Mode
#define Timer2_CH1_Mode(x)															 TMR2->chctrl[1]  = x ; 

// Timer2 Interrupt Enable
#define  Timer2_Interrupt_Enable(x)											TMR2->inten |= x  

// Timer2 Interrupt Disable
#define  Timer2_Interrupt_Disable(x)										TMR2->inten &= (~x) 

//Timer2 Start Enable
#define  Timer2_Start_Enable(x)														TMR2->chen |= x  

//Timer2 Start Disable
#define  Timer2_Start_Disable(x)													TMR2->chen &= (~x)  

/*
*************************************************************************************
*  LCM
*
*************************************************************************************
*/

/* LCM clock enable */
#define En_LCM_clk()																			CLKC->rsbepclkc[0] |= LCMEN

/*	LCM on	*/
#define LCM_on()																						LCM->control1 = 0x01;

/*	LCM off	*/
#define LCM_off()																						LCM->control1 = 0x00;


/* Set PD4 as COM3 */
#define Set_PD4_COM3()	                            	PD->gpio_ctrl[1] |= BIT4 ; PD->gpio_ctrl[0] |= BIT4
                                                                        
/* Set PD5 as COM2 */                                  
#define Set_PD5_COM2()	                            	PD->gpio_ctrl[1] |= BIT5 ; PD->gpio_ctrl[0] |= BIT5
                                                                        
/* Set PD6 as COM1 */                                  
#define Set_PD6_COM1()	                            	PD->gpio_ctrl[1] |= BIT6 ; PD->gpio_ctrl[0] |= BIT6
                                                                        
/* Set PD7 as COM0 */                                  
#define Set_PD7_COM0()	                            	PD->gpio_ctrl[1] |= BIT7 ; PD->gpio_ctrl[0] |= BIT7
                                                                        
/* Set PD0 as SEG03 */                                  
#define Set_PD0_SEG03()                            	PD->gpio_ctrl[1] |= BIT0 ; PD->gpio_ctrl[0] |= BIT0
                                                                        
/* Set PD1 as SEG02 */                                  
#define Set_PD1_SEG02()                            	PD->gpio_ctrl[1] |= BIT1 ; PD->gpio_ctrl[0] |= BIT1
                                                                        
/* Set PD2 as SEG01 */                                  
#define Set_PD2_SEG01()                            	PD->gpio_ctrl[1] |= BIT2 ; PD->gpio_ctrl[0] |= BIT2
                                                                        
/* Set PD3 as SEG00 */                                  
#define Set_PD3_SEG00()                            	PD->gpio_ctrl[1] |= BIT3 ; PD->gpio_ctrl[0] |= BIT3
                                                                        
/* Set PC0 as SEG11 */                                  
#define Set_PC0_SEG11()	                            	PC->gpio_ctrl[1] |= BIT0 ; PC->gpio_ctrl[0] |= BIT0
                                                                        
/* Set PC1 as SEG10 */                                  
#define Set_PC1_SEG10()	                            	PC->gpio_ctrl[1] |= BIT1 ; PC->gpio_ctrl[0] |= BIT1
                                                                        
/* Set PB6 as SEG13 */                                  
#define Set_PB6_SEG13()	                            	PB->gpio_ctrl[1] |= BIT6 ; PB->gpio_ctrl[0] |= BIT6
                                                                        
/* Set PB7 as SEG12 */                                  
#define Set_PB7_SEG12()	                            	PB->gpio_ctrl[1] |= BIT7 ; PB->gpio_ctrl[0] |= BIT7


/*
*************************************************************************************
*  SDM
*
*************************************************************************************
*/

// Enable SDM Clock
#define En_SDM_clk()																			CLKC->rsbepclkc[0] |= SDMEN

// Set PD4 as AP0
#define Set_PD4_AP0()																				PD->gpio_ctrl[1] |= BIT4 ; PD->gpio_ctrl[0] &= (~BIT4)

// Set PD5 as AN0
#define Set_PD5_AN0()																			PD->gpio_ctrl[1] |= BIT5 ; PD->gpio_ctrl[0] &= (~BIT5)

// Set PD6 as AP1
#define Set_PD6_AP1()																				PD->gpio_ctrl[1] |= BIT6 ; PD->gpio_ctrl[0] &= (~BIT6)

// Set PD7 as AN1
#define Set_PD7_AN1()																				PD->gpio_ctrl[1] |= BIT7 ; PD->gpio_ctrl[0] &= (~BIT7)

// Set SDM Clock
#define Set_SDM_clk_1M()																CLKC->rsbepclkdiv[0] &= (~0x07) ; CLKC->rsbepclkdiv[0] |= 0 
#define Set_SDM_clk_500K()														CLKC->rsbepclkdiv[0] &= (~0x07) ; CLKC->rsbepclkdiv[0] |= 1
#define Set_SDM_clk_250K()														CLKC->rsbepclkdiv[0] &= (~0x07) ; CLKC->rsbepclkdiv[0] |= 2
#define Set_SDM_clk_125K()														CLKC->rsbepclkdiv[0] &= (~0x07) ; CLKC->rsbepclkdiv[0] |= 3
#define Set_SDM_clk_62K()															CLKC->rsbepclkdiv[0] &= (~0x07) ; CLKC->rsbepclkdiv[0] |= 4
#define Set_SDM_clk_31M()															CLKC->rsbepclkdiv[0] &= (~0x07) ; CLKC->rsbepclkdiv[0] |= 5


// Set SDM OSR 
#define OSR_32768() 																	SDM->osr = 0;
#define OSR_16384() 																	SDM->osr = 1;
#define OSR_8192() 																		SDM->osr = 2;
#define OSR_4096()	 																	SDM->osr = 3;
#define OSR_2048() 																		SDM->osr = 4;
#define OSR_1024()	 																	SDM->osr = 5;
#define OSR_512() 																			SDM->osr = 6;
#define OSR_256() 																			SDM->osr = 7;
#define OSR_128()		 																	SDM->osr = 8;

// Set Input Channel
#define Set_input_channel_Ch0()									SDM->inmux = 0x00 ; SDM->inmux |= 0x80 	
#define Set_input_channel_Ch1()									SDM->inmux = 0x09 ; SDM->inmux |= 0x80
#define Set_input_channel_Ch2()									SDM->inmux = 0x12 ; SDM->inmux |= 0x80
#define Set_input_channel_Ch3()									SDM->inmux = 0x1B ; SDM->inmux |= 0x80
#define Set_input_channel_Ch4()									SDM->inmux = 0x24 ; SDM->inmux |= 0x80
#define Set_input_channel_Ch5()									SDM->inmux = 0x2D ; SDM->inmux |= 0x80
#define Set_input_channel_Ch6()									SDM->inmux = 0x36 ; SDM->inmux |= 0x80
#define Set_input_channel_Ch7()									SDM->inmux = 0x3F ; SDM->inmux |= 0x80

// Set Vref 
#define Set_Vref_PR0()																SDM->rmux = 0x00 ; SDM->rmux |= 0x80 			
#define Set_Vref_PR1()																SDM->rmux = 0x05 ; SDM->rmux |= 0x80
#define Set_Vref_1p2V()															SDM->rmux = 0x0A ; SDM->rmux |= 0x80
#define Set_Vref_1p0V()															SDM->rmux = 0x0F ; SDM->rmux |= 0x80

// Set PGA Gain
#define Set_PGA_Gain_x1()												SDM->pgaset &= (~0x07)  ;  SDM->pgaset |= 0
#define Set_PGA_Gain_x2()												SDM->pgaset &= (~0x07)  ;  SDM->pgaset |= 1
#define Set_PGA_Gain_x4()												SDM->pgaset &= (~0x07)  ;  SDM->pgaset |= 2
#define Set_PGA_Gain_x8()												SDM->pgaset &= (~0x07)  ;  SDM->pgaset |= 3
#define Set_PGA_Gain_x16()											SDM->pgaset &= (~0x07)  ;  SDM->pgaset |= 4
#define Set_PGA_Gain_x32()											SDM->pgaset &= (~0x07)  ;  SDM->pgaset |= 5
#define Set_PGA_Gain_x64()											SDM->pgaset &= (~0x07)  ;  SDM->pgaset |= 6
#define Set_PGA_Gain_x128()										SDM->pgaset &= (~0x07)  ;  SDM->pgaset |= 7

//Enable Input buffer
#define Enable_Input_buffer()											SDM->pgaset |= INBUF ; 

//Enable PGA chopper
#define Enable_PGA_chopper()										SDM->pgaset |= ENPGACH ; 

//Enable Vref buffer
#define Enable_Vref_buffer()												SDM->pgaset |= VRBUF ; 

//Enable Input buffer chopper
#define Enable_Input_buffer_chopper()				SDM->pgaset |= ENBUFCH ; 

//Disable Input buffer
#define Disable_Input_buffer()											SDM->pgaset &= (~INBUF ); 

//Disable PGA chopper
#define Disable_PGA_chopper()									SDM->pgaset &= (~ENPGACH) ; 

//Disable Vref buffer
#define Disable_Vref_buffer()											SDM->pgaset &= (~VRBUF) ;

//Disable Input buffer chopper
#define Disable_Input_buffer_chopper()				SDM->pgaset &= (~ENBUFCH) ; 

// Set ADC Gain
#define Set_ADC_Gain_x1()												SDM->encfg &= (~0x0F) ;  SDM->encfg |= 0; 		SDM->encfg |= 0x80
#define Set_ADC_Gain_x2()												SDM->encfg &= (~0x0F) ;  SDM->encfg |= 1; 		SDM->encfg |= 0x80
#define Set_ADC_Gain_x4()												SDM->encfg &= (~0x0F) ;  SDM->encfg |= 3;		SDM->encfg |= 0x80
#define Set_ADC_Gain_x8()												SDM->encfg &= (~0x0F) ;  SDM->encfg |= 7;		SDM->encfg |= 0x80
#define Set_ADC_Gain_x16()											SDM->encfg &= (~0x0F) ;  SDM->encfg |= 15;	SDM->encfg |= 0x80

// Enable ADC chopper
#define Enable_ADC_chopper()										SDM->encfg |=	ENADCCH

// Set Vref Gain
#define Set_Vref_Gain_x1()													SDM->encfg &=	(~0x30)	;	SDM->encfg |= 0x00	
#define Set_Vref_Gain_x1_div2()								SDM->encfg &=	(~0x30)	;	SDM->encfg |= 0x10
#define Set_Vref_Gain_x3_div4()								SDM->encfg &=	(~0x30)	;	SDM->encfg |= 0x20
#define Set_Vref_Gain_x1_div4()								SDM->encfg &=	(~0x30)	;	SDM->encfg |= 0x30

// Set DCSET
#define Set_DCSET_0()															SDM->adcset = 0
#define Set_DCSET_x1_div16_xVref()				SDM->adcset = 1
#define Set_DCSET_x2_div16_xVref()				SDM->adcset = 2
#define Set_DCSET_x3_div16_xVref()				SDM->adcset = 3
#define Set_DCSET_x4_div16_xVref()				SDM->adcset = 4
#define Set_DCSET_x5_div16_xVref()				SDM->adcset = 5		
#define Set_DCSET_x6_div16_xVref()				SDM->adcset = 6
#define Set_DCSET_x7_div16_xVref()				SDM->adcset = 7

//Enable ADC
#define Enable_ADC()																	SDM->encfg |= 0x80

// Enable TMPSNS 
#define Enable_TMPSNS() 													SDM->conf |= ENTMPSNS

// Enable INSC
#define Enable_INSC()																SDMTM->entest |= INSC

// Disable INSC
#define Disable_INSC()																SDMTM->entest &= (~INSC)

// Enable SDM interrupt
#define Enable_SDM_inerrupt()										SDM->intstat |= INTEN__

// Disable SDM interrupt
#define Disable_SDM_interrupt()									SDM->intstat &= (~INTEN__)


/*
*************************************************************************************
*  ANA
*
*************************************************************************************
*/

// Enable ANA Clock
#define En_ANA_clk()																			CLKC->rsbepclkc[0] |= ANAEN

// Enable BIAS
#define Enable_BIAS()																			ANA->pwrcfg |= ENBIAS

// Enable LDOA
#define Enable_LDOA()																		ANA->pwrcfg |= ENLDOA

// Enable VCM
#define Enable_VCM()																			ANA->pwrcfg |= ENVCM

// Control ENPDET
#define Enable_ENPDET()																ANA->pwrcfg |= ENPDET
#define Disable_ENPDET()																ANA->pwrcfg &= (~ENPDET)

// Control ENBODP
#define Enable_ENBODP()																ANA->pwrcfg |= ENBODP
#define Disable_ENBODP()																ANA->pwrcfg &= (~ENBODP)

// Control ENBODN
#define Enable_ENBODN()																ANA->pwrcfg |= ENBODN
#define Disable_ENBODN()															ANA->pwrcfg &= (~ENBODN)

// Control ENOPAMP
#define Enable_ENOPAMP()																ANA->pwrcfg |= ENOPAMP
#define Disable_ENOPAMP()															ANA->pwrcfg &= (~ENOPAMP)

// Control DAC1P
#define Enable_DAC1P()																ANA->igen_ctrl |= DAC1P
#define Disable_DAC1P()															ANA->igen_ctrl &= (~DAC1P)

// Control DAC2P
#define Enable_DAC2P()																ANA->igen_ctrl |= DAC2P
#define Disable_DAC2P()															ANA->igen_ctrl &= (~DAC2P)

// Control DAC1N
#define Enable_DAC1N()																ANA->igen_ctrl |= DAC1N
#define Disable_DAC1N()															ANA->igen_ctrl &= (~DAC1N)

// Control DAC2N
#define Enable_DAC2N()																ANA->igen_ctrl |= DAC2N
#define Disable_DAC2N()															ANA->igen_ctrl &= (~DAC2N)

// Control PSW
#define Enable_PSW()																ANA->igen_ctrl |= PSW
#define Disable_PSW()															ANA->igen_ctrl &= (~PSW)

// Enable IDAC1
#define Enable_IDAC1()																ANA->igen1 |= 0x80

// Enable IDAC2
#define Enable_IDAC2()																ANA->igen2 |= 0x80

// Disable IDAC1
#define Disable_IDAC1()																ANA->igen1 &= (~0x80)

// Disable IDAC2
#define Disable_IDAC2()																ANA->igen2 &= (~0x80)

//Set IDACx Current
#define Current_10uA																			0
#define Current_20uA																			1
#define Current_30uA																			2
#define Current_50uA																			4
#define Current_100uA																		8
#define Current_180uA																		16
#define Current_330uA																		32
#define Current_600uA																		64
#define Current_1200uA																	127

//Set IDAC1 Current
#define Set_IDAC1_Current(x)												ANA->igen1 |=	x

//Set IDAC2 Current
#define Set_IDAC2_Current(x)												ANA->igen2 |=	x


/*
*************************************************************************************
*  CAP   
*
*************************************************************************************
*/

// Enable CAP Clock
#define  En_CAP_clk()                                 CLKC->rsbepclkc[2] |= CAPEN

//	Set PD0 as CAP0
#define Set_PD0_CAP0()														PD->gpio_ctrl[1] &= (~BIT0) ; PD->gpio_ctrl[0] |= BIT0

//	Set PD1 as CAP1
#define Set_PD1_CAP1()														PD->gpio_ctrl[1] &= (~BIT1) ; PD->gpio_ctrl[0] |= BIT1

//	Set PD2 as CAP2
#define Set_PD2_CAP2()														PD->gpio_ctrl[1] &= (~BIT2) ; PD->gpio_ctrl[0] |= BIT2

//	Set PD3 as CAP3
#define Set_PD3_CAP3()														PD->gpio_ctrl[1] &= (~BIT3) ; PD->gpio_ctrl[0] |= BIT3


//	Set CAP0 LPF
#define Set_CAP0_LPF_1()														CAP->lpf_sel &= (~0x03)	;		CAP->lpf_sel	|= 0
#define Set_CAP0_LPF_2()														CAP->lpf_sel &= (~0x03)	;		CAP->lpf_sel	|= 1
#define Set_CAP0_LPF_3()														CAP->lpf_sel &= (~0x03)	;		CAP->lpf_sel	|= 2
#define Set_CAP0_LPF_4()														CAP->lpf_sel &= (~0x03)	;		CAP->lpf_sel	|= 3

//	Set CAP1 LPF
#define Set_CAP1_LPF_1()														CAP->lpf_sel &= (~0x0C)	;		CAP->lpf_sel	|= 0
#define Set_CAP1_LPF_2()														CAP->lpf_sel &= (~0x0C)	;		CAP->lpf_sel	|= 0x04
#define Set_CAP1_LPF_3()														CAP->lpf_sel &= (~0x0C)	;		CAP->lpf_sel	|= 0x08
#define Set_CAP1_LPF_4()														CAP->lpf_sel &= (~0x0C)	;		CAP->lpf_sel	|= 0x0C

//	Set CAP2 LPF
#define Set_CAP2_LPF_1()														CAP->lpf_sel &= (~0x30)	;		CAP->lpf_sel	|= 0x00
#define Set_CAP2_LPF_2()														CAP->lpf_sel &= (~0x30)	;		CAP->lpf_sel	|= 0x10
#define Set_CAP2_LPF_3()														CAP->lpf_sel &= (~0x30)	;		CAP->lpf_sel	|= 0x20
#define Set_CAP2_LPF_4()														CAP->lpf_sel &= (~0x30)	;		CAP->lpf_sel	|= 0x30

//	Set CAP3 LPF
#define Set_CAP3_LPF_1()														CAP->lpf_sel &= (~0xC0)	;		CAP->lpf_sel	|= 0x00
#define Set_CAP3_LPF_2()														CAP->lpf_sel &= (~0xC0)	;		CAP->lpf_sel	|= 0x40
#define Set_CAP3_LPF_3()														CAP->lpf_sel &= (~0xC0)	;		CAP->lpf_sel	|= 0x80
#define Set_CAP3_LPF_4()														CAP->lpf_sel &= (~0xC0)	;		CAP->lpf_sel	|= 0xC0

// Set CAP0 Mode
#define Set_CAP0_Mode_Edge()																CAP->mode &= (~0x03)	;  CAP->mode |= 0x00
#define Set_CAP0_Mode_RaisingToFalling()							CAP->mode &= (~0x03)	;  CAP->mode |= 0x01
#define Set_CAP0_Mode_FallingToRaising()							CAP->mode &= (~0x03)	;  CAP->mode |= 0x02
#define Set_CAP0_Mode_FallingToFalling()							CAP->mode &= (~0x03)	;  CAP->mode |= 0x03

// Set CAP1 Mode
#define Set_CAP1_Mode_Edge()																CAP->mode &= (~0x0C)	;  CAP->mode |= 0x00
#define Set_CAP1_Mode_RaisingToFalling()							CAP->mode &= (~0x0C)	;  CAP->mode |= 0x04
#define Set_CAP1_Mode_FallingToRaising()							CAP->mode &= (~0x0C)	;  CAP->mode |= 0x08
#define Set_CAP1_Mode_FallingToFalling()							CAP->mode &= (~0x0C)	;  CAP->mode |= 0x0C

// Set CAP2 Mode
#define Set_CAP2_Mode_Edge()																CAP->mode &= (~0x30)	;  CAP->mode |= 0x00
#define Set_CAP2_Mode_RaisingToFalling()							CAP->mode &= (~0x30)	;  CAP->mode |= 0x10
#define Set_CAP2_Mode_FallingToRaising()							CAP->mode &= (~0x30)	;  CAP->mode |= 0x20
#define Set_CAP2_Mode_FallingToFalling()							CAP->mode &= (~0x30)	;  CAP->mode |= 0x30

// Set CAP3 Mode
#define Set_CAP3_Mode_Edge()																CAP->mode &= (~0xC0)	;  CAP->mode |= 0x00
#define Set_CAP3_Mode_RaisingToFalling()							CAP->mode &= (~0xC0)	;  CAP->mode |= 0x40
#define Set_CAP3_Mode_FallingToRaising()							CAP->mode &= (~0xC0)	;  CAP->mode |= 0x80
#define Set_CAP3_Mode_FallingToFalling()							CAP->mode &= (~0xC0)	;  CAP->mode |= 0xC0

// Eanble CAP0  Interrupt 
#define Enable_Cap0_interrupt()																		CAP->inten |= 0x03;
#define Disable_Cap0_interrupt()																		CAP->inten &= (~0x03);

// Eanble CAP1  Interrupt
#define Enable_Cap1_interrupt()																		CAP->inten |= 0x0C;
#define Disable_Cap1_interrupt()																		CAP->inten &= (~0x0C);

// Eanble CAP2  Interrupt
#define Enable_Cap2_interrupt()																		CAP->inten |= 0x30;
#define Disable_Cap2_interrupt()																		CAP->inten &= (~0x30);

// Eanble CAP3  Interrupt
#define Enable_Cap3_interrupt()																		CAP->inten |= 0xC0;
#define Disable_Cap3_interrupt()																		CAP->inten &= (~0xC0);

// Enable CAP0
#define	Enable_CAP0()																								CAP->cap_ctrl |= 0x10;

// Enable CAP1
#define	Enable_CAP1()																								CAP->cap_ctrl |= 0x20;

// Disable CAP1
#define Disable_CAP1()																							CAP->cap_ctrl &= (~0x20);

// Enable CAP2
#define	Enable_CAP2()																								CAP->cap_ctrl |= 0x40;

// Enable CAP3
#define	Enable_CAP3()																								CAP->cap_ctrl |= 0x80;

/*
*************************************************************************************
*  MFA   
*
*************************************************************************************
*/

//	Enable MFA clock 
#define  En_MFA_clk()                                 CLKC->rsbepclkc[2] |= MFAEN

/*
*************************************************************************************
*  FMC   
*
*************************************************************************************
*/

// Enable FMC clock
#define En_FMC_clk()																	CLKC->rsbpclkc |= FMCEN

//Disable FMC clock
#define Disable_FMC_clk()													CLKC->rsbpclkc &= (~FMCEN)

// Enable information block 
#define Enable_information_block()						FMC->fmccon = 0x60;   

// Disable information block 
#define Disable_information_block()						FMC->fmccon = 0x20; 

/*
*************************************************************************************
*  EINT   
*
*************************************************************************************
*/

//Enable EINT Clock
#define  En_EINT_clk()                                 CLKC->rsbepclkc[2] |= EINTEN

//Set EINT  Interrupt Sampling Clock as LSRC
#define Set_EINT_ClockSource_LSRC()			CLKC->clksel |= 0x10;	

//Set EINT  Interrupt Sampling Clock as PFB
#define Set_EINT_ClockSource_PFB()					CLKC->clksel &= (~BIT4);	

//Set PB3 As EINT0
#define Set_PB3_EINT0()															PB->gpio_ctrl[1] |= BIT3 ; PB->gpio_ctrl[0] &= (~BIT3)

//Set PA5 As EINT1
#define Set_PA5_EINT1()															PA->gpio_ctrl[1] |= BIT5 ; PA->gpio_ctrl[0] &= (~BIT5)

//Set PA3 As EINT2
#define Set_PA3_EINT2()															PA->gpio_ctrl[1] |= BIT3 ; PA->gpio_ctrl[0] &= (~BIT3)

//Set PA2 As EINT3
#define Set_PA2_EINT3()															PA->gpio_ctrl[1] |= BIT2 ; PA->gpio_ctrl[0] &= (~BIT2)

//Set EINT0 Mode
#define Set_EINT0_Falling_and_Low()			 INTC->eint_ctrl &=  (~0x03); 	INTC->eint_ctrl |= 0x00;  
#define Set_EINT0_Rising()												 INTC->eint_ctrl &=  (~0x03);   INTC->eint_ctrl |= 0x01;
#define Set_EINT0_Falling()												 INTC->eint_ctrl &=  (~0x03);		INTC->eint_ctrl |= 0x02;
#define Set_EINT0_Rising_and_Falling()		 INTC->eint_ctrl &=  (~0x03);		INTC->eint_ctrl |= 0x03;

//Set EINT1 Mode
#define Set_EINT1_Falling_and_Low()			 INTC->eint_ctrl &=  (~0x0C); 	INTC->eint_ctrl |= 0x00;  
#define Set_EINT1_Rising()												 INTC->eint_ctrl &=  (~0x0C);  INTC->eint_ctrl |= 0x04;
#define Set_EINT1_Falling()												 INTC->eint_ctrl &=  (~0x0C);	INTC->eint_ctrl |= 0x08;
#define Set_EINT1_Rising_and_Falling()		 INTC->eint_ctrl &=  (~0x0C);	INTC->eint_ctrl |= 0x0C;

//Set EINT2 Mode
#define Set_EINT2_Falling_and_Low()			 INTC->eint_ctrl &=  (~0x30); 	INTC->eint_ctrl |= 0x00;  
#define Set_EINT2_Rising()												 INTC->eint_ctrl &=  (~0x30);   INTC->eint_ctrl |= 0x10;
#define Set_EINT2_Falling()												 INTC->eint_ctrl &=  (~0x30);		INTC->eint_ctrl |= 0x20;
#define Set_EINT2_Rising_and_Falling()		 INTC->eint_ctrl &=  (~0x30);		INTC->eint_ctrl |= 0x30;

//Set EINT3 Mode
#define Set_EINT3_Falling_and_Low()			 INTC->eint_ctrl &=  (~0xC0); 	INTC->eint_ctrl |= 0x00;  
#define Set_EINT3_Rising()												 INTC->eint_ctrl &=  (~0xC0);  INTC->eint_ctrl |= 0x40;
#define Set_EINT3_Falling()												 INTC->eint_ctrl &=  (~0xC0);	INTC->eint_ctrl |= 0x80;
#define Set_EINT3_Rising_and_Falling()		 INTC->eint_ctrl &=  (~0xC0);	INTC->eint_ctrl |= 0xC0;

//Set EINT0 interrupt_
#define Enable_EINT0_interrupt()								INTC->eint_en |= 0x01;

//Set EINT1 interrupt_
#define Enable_EINT1_interrupt()								INTC->eint_en |= 0x02;

//Set EINT2 interrupt_
#define Enable_EINT2_interrupt()								INTC->eint_en |= 0x04;

//Set EINT3 interrupt_
#define Enable_EINT3_interrupt()								INTC->eint_en |= 0x08;

//Disable EINT3 interrupt_
#define Disable_EINT3_interrupt()								INTC->eint_en &= (~0x08);

/*
*************************************************************************************
*  SPI
*
*************************************************************************************
*/

//Enable SPI Clock
#define En_SPI_clk()																			CLKC->rsbepclkc[1] |= SPIEN

//Set PA0 as MISO
#define Set_PA0_MISO()															PA->gpio_ctrl[1] &= (~BIT0) ; PA->gpio_ctrl[0] |= BIT0

//Set PA1 as MOSI
#define Set_PA1_MOSI()															PA->gpio_ctrl[1] &= (~BIT1) ; PA->gpio_ctrl[0] |= BIT1

//Ser PA2 as SCLK
#define Set_PA2_SCLK()															PA->gpio_ctrl[1] &= (~BIT2) ; PA->gpio_ctrl[0] |= BIT2

//Ser PA3 as SS
#define Set_PA3_SS()																		PA->gpio_ctrl[1] &= (~BIT3) ; PA->gpio_ctrl[0] |= BIT3

//Clock(HSRC = 8M Hz) 
#define SPI_Clock_1M()															 SPI->intf_timing[0] = 0x03;   
#define SPI_Clock_2M()															 SPI->intf_timing[0] = 0x01; 
#define SPI_Clock_4M()															 SPI->intf_timing[0] = 0x00;   



#endif 
                                                                                                 
