C51 COMPILER V9.60.0.0   MAIN                                                              03/15/2023 13:48:04 PAGE 1   


C51 COMPILER V9.60.0.0, COMPILATION OF MODULE MAIN
OBJECT MODULE PLACED IN .\Release\main.obj
COMPILER INVOKED BY: C:\Keil_v5\C51\BIN\C51.EXE main.c OPTIMIZE(0,SPEED) REGFILE(.\Release\Sample_DrvTMR.ORC) BROWSE INC
                    -DIR(..\..\..\..\C51SIS\C51;..\..\..\Include\Driver) DEBUG OBJECTEXTEND TABS(2) OBJECT(.\Release\main.obj)

line level    source

   1          /**************************************************************************//**
   2           * @file           main.c
   3           * @version        V1.0
   4           * $Revision:      1 $
   5           * $Date:          2017/01/04 $
   6           * @brief          Main function
   7           * @Author         Jeffrey Kang
   8           * @ContactInfo    chkang@esmt.com.tw
   9           *
  10           * @note
  11           *
  12           * Copyright (C) 1998 Elite Semiconductor Memory Technology Corp.
  13           * All rights reserved.
  14           *
  15           ******************************************************************************/
  16          
  17          
  18          #include <REG52.h>
  19          #include "system_FE81001.h"
  20          
  21          
  22          #define TMR  // TMR or PWM
  23          
  24          
  25          volatile unsigned char cnt = 0;
  26          
  27          /**
  28           * @brief       delay function
  29           *
  30           * @param       None
  31           *
  32           * @return      None
  33           *
  34           * @details     1. 
  35           */
  36          void delay( void )
  37          {
  38   1        unsigned int i;
  39   1        
  40   1        for( i = 0 ; i < 500 ; i++ ){}
  41   1      }
  42          
  43          
  44          /**
  45           * @brief       TMR2ISR function
  46           *
  47           * @param       None
  48           *
  49           * @return      None
  50           *
  51           * @details     1. 
  52           */
  53          const void TMR2ISR (void) interrupt ISR_TMR2
  54          {
C51 COMPILER V9.60.0.0   MAIN                                                              03/15/2023 13:48:04 PAGE 2   

  55   1        unsigned char int_stat;
  56   1        
  57   1        /* read interrupt status */
  58   1        int_stat = TMR2->int_stat;
  59   1        TMR2->int_stat = 0xFF;
  60   1        
  61   1        /*Toggle LED*/
  62   1         PD3 = ~PD3;
  63   1        
  64   1        /* enable global interrupt */
  65   1        INTC->int_gmask = 0x01;
  66   1      }
  67          
  68          
  69          /**
  70           * @brief       TMR1ISR function
  71           *
  72           * @param       None
  73           *
  74           * @return      None
  75           *
  76           * @details     1. 
  77           */
  78          const void TMR1ISR (void) interrupt ISR_TMR1
  79          {
  80   1        unsigned char int_stat;
  81   1        
  82   1        /* read interrupt status */
  83   1        int_stat = TMR1->int_stat;
  84   1        TMR1->int_stat = 0xFF;
  85   1        
  86   1        /*Toggle LED*/
  87   1         PD2 = ~PD2;
  88   1        
  89   1        /* enable global interrupt */
  90   1        INTC->int_gmask = 0x01;
  91   1      
  92   1      }
  93          
  94          
  95          /**
  96           * @brief       TMR0ISR function
  97           *
  98           * @param       None
  99           *
 100           * @return      None
 101           *
 102           * @details     1. 
 103           */
 104          const void TMR0ISR (void) interrupt ISR_TMR0
 105          {
 106   1        unsigned char int_stat;
 107   1      
 108   1        /* read interrupt status */
 109   1           int_stat = TMR0->int_stat;
 110   1          TMR0->int_stat = 0xFF;      // Write 1 to Clear
 111   1        
 112   1           PD1 = ~PD1;
 113   1      
 114   1        /* enable global interrupt */
 115   1           INTC->int_gmask = 0x01;
 116   1      }
C51 COMPILER V9.60.0.0   MAIN                                                              03/15/2023 13:48:04 PAGE 3   

 117          
 118          
 119          /**
 120           * @brief       TMR2Init function
 121           *
 122           * @param       None
 123           *
 124           * @return      None
 125           *
 126           * @details     1. 
 127           */
 128          void TMR2Init(void)
 129          {
 130   1        
 131   1      #ifdef TMR
 132   1        
 133   1        /* TMR2 control setting */
 134   1        Timer2_CH0_Mode(Mode_32bit_Timer);
 135   1        Timer2_CH1_Mode(Mode_32bit_Timer);
 136   1        
 137   1        /* TMR2 Ch0 reload setting*/
 138   1        TMR2->reload0[0] = 0x00;      // 32-bit Timers : Reload0_0 = 0x00 (0xF4240 -> 1,000,000) MSB
 139   1        TMR2->reload0[1] = 0x0F;      // 32-bit Timers : Reload0_1 = 0x0F (0xF4240 -> 1,000,000)
 140   1        TMR2->reload0[2] = 0x42;      // 32-bit Timers : Reload0_2 = 0x42 (0xF4240 -> 1,000,000)
 141   1        TMR2->reload0[3] = 0x40;      // 32-bit Timers : Reload0_3 = 0x40 (0xF4240 -> 1,000,000)  LSB
 142   1        
 143   1        /* TMR2 Ch1 reload setting*/
 144   1        TMR2->reload1[0] = 0x00;      // 32-bit Timers : Reload0_0 = 0x00 (0xF4240 -> 1,000,000) MSB
 145   1        TMR2->reload1[1] = 0x0F;      // 32-bit Timers : Reload0_1 = 0x0F (0xF4240 -> 1,000,000)
 146   1        TMR2->reload1[2] = 0x42;      // 32-bit Timers : Reload0_2 = 0x42 (0xF4240 -> 1,000,000)
 147   1        TMR2->reload1[3] = 0x40;      // 32-bit Timers : Reload0_3 = 0x40 (0xF4240 -> 1,000,000)  LSB
 148   1        
 149   1        /* interrupt enable setting */
 150   1        Timer2_Interrupt_Enable(Ch0_Timer0);
 151   1        
 152   1        /* timer start */
 153   1        Timer2_Start_Enable(Ch0_Timer0);
 154   1        
 155   1      #else  // PWM
              
                  /* TMR2 control setting */
                Timer2_CH0_Mode(Mode_PWM);
                Timer2_CH1_Mode(Mode_PWM);
                
                /* TMR2 Ch0 reload setting */
                TMR2->reload0[0] = 0x00;      //  PWM High Level Width - H_byte =  0x00(99)
                TMR2->reload0[1] = 0x63;      //  PWM High Level Width - L_byte  =  0x63(99)
                TMR2->reload0[2] = 0x00;      //  PWM Low Level Width - H_byte  =  0x00(99)
                TMR2->reload0[3] = 0x63;      //  PWM Low Level Width - L_byte   =  0x63(99)
              
                /* TMR2 Ch1 reload setting */
                TMR2->reload1[0] = 0x03;      //  PWM High Level Width - H_byte =  0x03(999)
                TMR2->reload1[1] = 0xE7;      //  PWM High Level Width - L_byte  =  0xE7(999)
                TMR2->reload1[2] = 0x03;      //  PWM Low Level Width - H_byte  =  0x03(999)
                TMR2->reload1[3] = 0xE7;      //  PWM Low Level Width - L_byte   =  0xE7(999)
                
                /* interrupt enable setting */
                
                /* timer start */
                Timer2_Start_Enable(Ch0_Timer3 | Ch1_Timer3);
                
              #endif
C51 COMPILER V9.60.0.0   MAIN                                                              03/15/2023 13:48:04 PAGE 4   

 179   1      
 180   1      }
 181          
 182          
 183          /**
 184           * @brief       TMR1Init function
 185           *
 186           * @param       None
 187           *
 188           * @return      None
 189           *
 190           * @details     1. 
 191           */
 192          void TMR1Init(void)
 193          {
 194   1      #ifdef TMR
 195   1        
 196   1        /* TMR1 control setting */
 197   1        Timer1_CH0_Mode(Mode_32bit_Timer);
 198   1        Timer1_CH1_Mode(Mode_32bit_Timer);
 199   1        
 200   1        /* TMR1 Ch0 reload setting*/
 201   1        TMR1->reload0[0] = 0x00;      // 32-bit Timers : Reload0_0 = 0x00 (0xF4240 -> 1,000,000) MSB
 202   1        TMR1->reload0[1] = 0x0F;      // 32-bit Timers : Reload0_1 = 0x0F (0xF4240 -> 1,000,000)
 203   1        TMR1->reload0[2] = 0x42;      // 32-bit Timers : Reload0_2 = 0x42 (0xF4240 -> 1,000,000)
 204   1        TMR1->reload0[3] = 0x40;      // 32-bit Timers : Reload0_3 = 0x40 (0xF4240 -> 1,000,000)  LSB
 205   1        
 206   1        /* TMR1 Ch1 reload setting*/
 207   1        TMR1->reload1[0] = 0x00;      // 32-bit Timers : Reload0_0 = 0x00 (0xF4240 -> 1,000,000) MSB
 208   1        TMR1->reload1[1] = 0x0F;      // 32-bit Timers : Reload0_1 = 0x0F (0xF4240 -> 1,000,000)
 209   1        TMR1->reload1[2] = 0x42;      // 32-bit Timers : Reload0_2 = 0x42 (0xF4240 -> 1,000,000)
 210   1        TMR1->reload1[3] = 0x40;      // 32-bit Timers : Reload0_3 = 0x40 (0xF4240 -> 1,000,000)  LSB
 211   1        
 212   1        /* interrupt enable setting */
 213   1        Timer1_Interrupt_Enable(Ch0_Timer0);
 214   1        
 215   1        /* timer start */
 216   1        Timer1_Start_Enable(Ch0_Timer0);
 217   1        
 218   1      #else  // PWM
              
                  /* TMR1 control setting */
                Timer1_CH0_Mode(Mode_PWM);
                Timer1_CH1_Mode(Mode_PWM);
                
                /* TMR1 Ch0 reload setting */
                TMR1->reload0[0] = 0x00;      //  PWM High Level Width - H_byte =  0x00(99)
                TMR1->reload0[1] = 0x63;      //  PWM High Level Width - L_byte  =  0x63(99)
                TMR1->reload0[2] = 0x00;      //  PWM Low Level Width - H_byte  =  0x00(99)
                TMR1->reload0[3] = 0x63;      //  PWM Low Level Width - L_byte   =  0x63(99)
              
                /* TMR1 Ch1 reload setting */
                TMR1->reload1[0] = 0x03;      //  PWM High Level Width - H_byte =  0x03(999)
                TMR1->reload1[1] = 0xE7;      //  PWM High Level Width - L_byte  =  0xE7(999)
                TMR1->reload1[2] = 0x03;      //  PWM Low Level Width - H_byte  =  0x03(999)
                TMR1->reload1[3] = 0xE7;      //  PWM Low Level Width - L_byte   =  0xE7(999)
                
                /* interrupt enable setting */
                
                /* timer start */
                Timer1_Start_Enable(Ch0_Timer3 | Ch1_Timer3);
                
C51 COMPILER V9.60.0.0   MAIN                                                              03/15/2023 13:48:04 PAGE 5   

              #endif
 242   1      }
 243          
 244          
 245          /**
 246           * @brief       TMR0Init function
 247           *
 248           * @param       None
 249           *
 250           * @return      None
 251           *
 252           * @details     1. 
 253           */
 254          void TMR0Init(void)
 255          {
 256   1      #ifdef TMR
 257   1        
 258   1        /* TMR0 control setting */
 259   1        Timer0_CH0_Mode(Mode_32bit_Timer);
 260   1        Timer0_CH1_Mode(Mode_32bit_Timer);
 261   1        
 262   1        /* TMR0 Ch0 reload setting*/
 263   1        TMR0->reload0[0] = 0x00;      // 32-bit Timers : Reload0_0 = 0x00 (0xF4240 -> 1,000,000) MSB
 264   1        TMR0->reload0[1] = 0x0F;      // 32-bit Timers : Reload0_1 = 0x0F (0xF4240 -> 1,000,000)
 265   1        TMR0->reload0[2] = 0x42;      // 32-bit Timers : Reload0_2 = 0x42 (0xF4240 -> 1,000,000)
 266   1        TMR0->reload0[3] = 0x40;      // 32-bit Timers : Reload0_3 = 0x40 (0xF4240 -> 1,000,000)  LSB
 267   1        
 268   1        /* TMR0 Ch1 reload setting*/
 269   1        TMR0->reload1[0] = 0x00;      // 32-bit Timers : Reload1_0 = 0x00 (0xF4240 -> 1,000,000) MSB
 270   1        TMR0->reload1[1] = 0x0F;      // 32-bit Timers : Reload1_1 = 0x0F (0xF4240 -> 1,000,000)
 271   1        TMR0->reload1[2] = 0x42;      // 32-bit Timers : Reload1_2 = 0x42 (0xF4240 -> 1,000,000)
 272   1        TMR0->reload1[3] = 0x40;      // 32-bit Timers : Reload1_3 = 0x40 (0xF4240 -> 1,000,000) LSB
 273   1        
 274   1        /* interrupt enable setting */
 275   1        Timer0_Interrupt_Enable(Ch0_Timer0);
 276   1        
 277   1        /* timer start */
 278   1        Timer0_Start_Enable(Ch0_Timer0);
 279   1        
 280   1      #else // PWM
              
                /* TMR0 control setting */
                Timer0_CH0_Mode(Mode_PWM);
                Timer0_CH1_Mode(Mode_PWM);
                
                /* TMR0 Ch0 reload setting */
                TMR0->reload0[0] = 0x00;      //  PWM High Level Width - H_byte =  0x00(99)
                TMR0->reload0[1] = 0x63;      //  PWM High Level Width - L_byte  =  0x63(99)
                TMR0->reload0[2] = 0x00;      //  PWM Low Level Width - H_byte  =  0x00(99)
                TMR0->reload0[3] = 0x63;      //  PWM Low Level Width - L_byte   =  0x63(99)
              
                /* TMR0 Ch1 reload setting */
                TMR0->reload1[0] = 0x03;      //  PWM High Level Width - H_byte =  0x03(999)
                TMR0->reload1[1] = 0xE7;      //  PWM High Level Width - L_byte  =  0xE7(999)
                TMR0->reload1[2] = 0x03;      //  PWM Low Level Width - H_byte  =  0x03(999)
                TMR0->reload1[3] = 0xE7;      //  PWM Low Level Width - L_byte   =  0xE7(999)
                
                /* interrupt enable setting */
                
                /* timer start */
                Timer0_Start_Enable(Ch0_Timer3 | Ch1_Timer3);
                
C51 COMPILER V9.60.0.0   MAIN                                                              03/15/2023 13:48:04 PAGE 6   

              #endif
 304   1      }
 305          
 306          
 307          /**
 308           * @brief       TMRClkInit function
 309           *
 310           * @param       None
 311           *
 312           * @return      None
 313           *
 314           * @details     1. 
 315           */
 316          void TMRClkInit (void)
 317          {
 318   1        /* TMR0, TMR1, TMR2, clock selection : 0 -> PCLK, 1 -> LSRC */
 319   1          Timer0_clock_PCLK();
 320   1        
 321   1        /* enable TMR0, TMR1, TMR2 clock divider */
 322   1          Timer0_clock_Div_4();
 323   1          Timer1_clock_Div_4();
 324   1          Timer2_clock_Div_4();
 325   1        
 326   1        /* enable TMR0, TMR1, TMR2 clock */
 327   1          //CLKC->rsbepclkc[1] |= 0x07;
 328   1          En_Timer0_clk();
 329   1          En_Timer1_clk();
 330   1          En_Timer2_clk();
 331   1      }
 332          
 333          
 334          /**
 335           * @brief       IOCFG function
 336           *
 337           * @param       None
 338           *
 339           * @return      None
 340           *
 341           * @details     1. 
 342           */
 343          void IOCFG( void )
 344          {
 345   1        /* enable GPIO clock */
 346   1        PORT_PAPBPCPD_Clock_Enable();
 347   1        
 348   1        /* enable PB.4 PB.5 PB.6 PB.7 output */
 349   1        PORT_SetPBPushPull(BIT4 | BIT5 | BIT6 | BIT7);
 350   1        
 351   1        /* enable PB.4 PB.5 PB.6 PB.7 PWM */
 352   1        Set_PB4_PWM0();
 353   1        Set_PB5_PWM1();
 354   1        Set_PB6_PWM2();
 355   1        Set_PB7_PWM3();
 356   1        
 357   1        /* enable PC.0 PC.1 output */
 358   1        PORT_SetPCPushPull(BIT0 | BIT1);
 359   1        
 360   1        /* enable PC.0 PC.1 PWM */
 361   1        Set_PC0_PWM4();
 362   1        Set_PC1_PWM5();
 363   1        
 364   1        /* Set PD1. ,PD2.,PD3 output */
C51 COMPILER V9.60.0.0   MAIN                                                              03/15/2023 13:48:04 PAGE 7   

 365   1        PORT_SetPDPushPull(BIT1 | BIT2 | BIT3 );
 366   1        
 367   1        /* Ini LED */
 368   1        PD1 = 0; // LED_G1 On
 369   1        PD2 = 1 ; //LED_R Off
 370   1        PD3= 0;  // LED_G2  On
 371   1        
 372   1      }
 373          
 374          
 375          /**
 376           * @brief       main function
 377           *
 378           * @param       None
 379           *
 380           * @return      None
 381           *
 382           * @details     1. 
 383           *              2.
 384           */
 385          int main( void )
 386          {
 387   1        IOCFG();
 388   1        
 389   1        /* enable TMR0, TMR1 clock */
 390   1        TMRClkInit();
 391   1        
 392   1        /* TMR0 init */
 393   1        TMR0Init();
 394   1        
 395   1        /* TMR1 init */
 396   1        TMR1Init();
 397   1        
 398   1        /* TMR2 init */
 399   1        TMR2Init();
 400   1        
 401   1        /* enable global interrupt */
 402   1        INTC->int_gmask = 0x01;
 403   1        
 404   1        while(1){
 405   2          delay();
 406   2        }
 407   1      }


MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =    836    ----
   CONSTANT SIZE    =   ----    ----
   XDATA SIZE       =   ----    ----
   PDATA SIZE       =   ----    ----
   DATA SIZE        =      6    ----
   IDATA SIZE       =   ----    ----
   BIT SIZE         =   ----    ----
END OF MODULE INFORMATION.


C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)
